A64
| A64 | |
|---|---|
 | |
| Manufacturer | Allwinner |
| Process | 40nm |
| CPU | Quad-Core ARM Cortex-A53 |
| Memory | LPDDR2/ LPDDR3/ DDR3 / DDR3L |
| GPU | Mali400 MP2 |
| Connectivity | |
| Video | MIPI DSI [email protected], LVDS [email protected], RGB [email protected], HDMI v1.4 [email protected] |
| Storage | NAND, NOR, MMC |
| USB | OTG, 1x Host |
| Release Date | ? |
| Website | Product Page |
Allwinner A64 (sun50i) SoC features a Quad-Core Cortex-A53 ARM CPU, and a Mali400 MP2 GPU from ARM.
Contents |
Overview
The A64 is basically an Allwinner H3 with the Cortex-A7 cores replaced with Cortex-A53 cores (ARM64 architecture). They share most of the memory map, clocks, interrupts and also uses the same IP blocks. Differences between the H3 and the A64 seem to be:
- The H3 has three USB host controllers, whereas the A64 has only one. Both SoCs have an additional USB-OTG controller, which is assumed to be used as normal host controller as well.
- The H3 DRAM controller supports up to 2GB of RAM, the A64 supports up to 3 GB. Despite being a 64-bit chip, this makes the SoC entirely 32-bit on the physical side.
- The H3 supports 5 UARTs, the A64 has 6 of them.
- The MMC controller has been updated to support faster transfer modes. The MMC clocks have changed on the way, now the MMC controller itself provides support for the output and sample phase.
A64 SoC Features
- CPU
- ARM Cortex-A53 Quad-Core (r0p4, revidr=0x80) (scroll down for the PDF link)
- 512KiB L2-Cache
- 32KiB (Instruction) / 32KiB (Data) L1-Cache per core
- SIMD NEON (including double-precision floating point), VFP4
- Cryptography Extension (SHA and AES instructions)
- Affected by one critical erratum (only in AArch64 state): 843419
- GPU
- ARM Mali400 MP2
- Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).
- Complies with OpenGL ES 2.0
- Memory
- DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 controller (up to 3GB of 667MHz(DDR-1333))
- NAND Flash controller and 64-bit ECC
- Video
- H.265 [email protected], [email protected] decoding
- H.264 [email protected] decoding
- MPEG 1/2/4: [email protected]
- VC1 [email protected]
- VP8 [email protected]
- AVS/AVS+ [email protected]
- JPEG/MJPEG [email protected]
- H.264 [email protected] encoding
- Display
- LVDS single link up to [email protected]
- RBG with DE/SYNC up to [email protected]
- MIPI DSI 4-lanes up to [email protected]
- HDMI1.4 with HDCP1.2 up to [email protected]
- Camera
- Supports parallel 8-bit YUV422 sensor
- Support CCIR656 protocol for NTSC and PAL
- Maximum still capture resolution 5M
- Maximum video capture resolution up to [email protected]
- PMIC
- X-Powers AXP803, as seen used with A64 in Olimex Olinuxino A64 design
Documentation
Some devices in the SoC are not described in the manual, but have descriptions in other SoC's manuals:
- RSB: MMIO address and IRQ mentioned in the A64 manual, IP description in the A83T manual.
- PRCM: MMIO address mentioned in the A64 manual, IP description in the A83T manual.
Some remarks about the memory map.
Register guide
Software
Original SDK
Boot0
U-boot
Allwinner
Sunxi Community
Mainline U-Boot
Basic support for the A64 SoC has been been merged into 2016.05-rc1. This covers UART, MMC and required GPIOs and clocks, but no Ethernet or USB yet. Also as there is no information on the DRAM controller so far, the SPL support is not enabled, so boot0 is required at the moment to get U-Boot loaded.
The U-Boot implementation is 64-bit (armv8), so an aarch64 cross compiler is needed to compile U-Boot.
Kernel code
Allwinner
Sunxi Community
Devices
Devices in development:
See also
References
